A half-pel motion estimation architecture for MPEG-4 applications

This paper presents a novel half-pel motion estimation architecture for MPEG-4 applications. The proposed architecture consists of two parts; interpolation part and full search block matching part. The first part computes the halfpel values by interpolation of the full pixels. The second part searches for the hest match to the reference block using full search block matching algorithm to enhance the video quality. The proposed architecture has been prototyped, simulated and synthesized for 0.16 pm CMOS technology using TSMC standard cells. At 50 MHz clock frequency the proposed architecture needs I20 psec to compute the motion vectors. The prototyped architecture consumes 247.04 mW with 1.6 V supply voltage and has core area of 0.703 mm2.